Phase locked loops (PLLs) have been used for frequency synthesis in many conventional circuits, and these PLLs generally included internal and/or external dividers. These PLLs (and the corresponding dividers) have also been used to generate fractional frequencies, but, usually, at a price (namely, spurs and jitter). Therefore, there is a need for an improved fractional divider that can be used with or within a PLL or reference clock generator.
Some examples of conventional circuits are: U.S. Pat. No. 6,114,914; U.S. Pat. No. 6,236,703; U.S. Pat. No. 6,807,552; U.S. Pat. No. 7,295,077; U.S. Pat. No. 7,417,510; U.S. Pat. No. 7,595,670; U.S. Pat. No. 7,764,134; U.S. Pat. No. 7,800,451; and Yang et al., “A High-Frequency Phase Compensation Fractional-N Frequency Synthesizer,” IEEE International Symposium on Circuits and Systems, 2005 ISCAS, May 23-26, 2005, pp. 5091-5094.